If We Are Using Pages Of Size 4kb, How Many Bits Are Needed For Displacement Into A Page?

The Operating Arrangement of a reckoner may periodically collect all the free memory space to form contiguous block of free space. This is called:

A	Concatenation
B	Garbage drove
C	Collision
D	Dynamic Memory Allocation

Question 1 Explanation:

Garbage collection (GC) is a class of automatic retention management. The garbage collector, or just collector, attempts to reclaim garbage, or retention occupied by objects that are no longer in use past the program.

There are few techniques for collecting the garbage

Mark and Sweep:
In this technique, Every object is marked and checked is information technology used or non. if it is not in used then swept information technology

Semi Space:
It is performed by ane infinite to the other infinite so that information technology becomes a new heap.

A computer has 1000 Thousand of main retentivity. The jobs arrive and finish in the sequence

Job 1 requiring 200 K arrives Job 2 requiring 350 K arrives Task 3 requiring 300 Thousand arrives Job i finishes Chore 4 requiring 120 K arrives Job v requiring 150 K arrives Task 6 requiring 80 K arrives

Amid the best fit and first fit, which performs meliorate for this sequence?

A	First fit
B	All-time fit
C	Both perform the same
D	None of the above

Question 2 Explanation:

Initial in that location is 1000k main memory available.
Then
Task 1 arrives and occupies 200k
Job ii arrives and occupies 350k
Chore iii arrives and occupies 300k (∴Assume continuous resource allotment)
Free Memory space is = Total space - Space occupied past Chore ane and Job 2 and Job3
That is 1000−(200+350+300)=1000-850=150k

Now Job 1 is completed. So that infinite became free,
Therefore 200k slot and 150k slots are free

Now job4 arrives which is of size 120k

First fit :
In Get-go fit Job4 occupy 200 k slot (free slot ) and now free is =200−120=80k,
Now Job 5 which is of size 150k go far which will occupy 150 k slot
Then, Job vi  of size 80k make it which volition occupy in 80k slot (200−120) then, all jobs volition be allocated successfully.

Best fit :
In best fit Job4  of size 120k will occupy best fit free space which is 150k then,
now remaining 150−120=30k,
Then Job5 of size 150k arrive and it will be occupied in 200k slot, which is all-time fit for this job.
So, free space =200−150=fifty,
Now, job6 of size 80k arrive, but there is no continuous 80k retention free. So, it will not be allocated successfully.

In All-time Fit, Job vi is unable to get the retentiveness for its execution.
Hence First Fit performs improve than all-time fit.

Consider a logical accost space of viii pages of 1024 words mapped into memory of 32 frames. How many bits are there in the logical accost?

A	13 bits
B	15 bits
C	xiv $.25
D	12 bits

Question iii Explanation:

****We know that folio and frame both have the same size***

Concrete Retention accept 32 frames = ii⁵
Size of word 1024 = 2¹⁰
Size of concrete address space = Number of frames × Frame size
Size of physical address infinite =2^v× 2^x= 2¹⁵
»» Number of required bits in the physical address =xv

Logical Memory take 8 pages = 2³
Size of word = 2¹⁰
Size of logical accost space = 2^{one thousand}
= Number of pages × page size
= 2^three × ii¹⁰ = 2¹³
»» chiliad=13 flake
»» Number of required bits in the logical address = 13 bits

Permit the folio error service time be 10 ms in a computer with average retention access fourth dimension being 20 ns. If the ane-page fault is generated for every ten⁶ retention accesses, what is the effective access time for the retentivity?

A	21.four ns
B	29.ix ns
C	23.5 ns
D	35.1 ns

A CPU generates 32-bit virtual addresses. The folio size is 4 KB The processor has a translation lookaside buffer (TLB) which can hold a total of 128 page table entries and is iv-way set associative. The minimum size of the TLB tag is:

A	eleven $.25
B	xiii bits
C	fifteen bits
D	twenty bits

Question five Explanation:

Given data,
Virtual addresses = 32 chip = 2⁵ fleck,
Page size =iv KB=2¹² B,
TLB can hold a total of 128 folio table entries
4-fashion prepare associative,

Size of a folio = 4KB = we tin write as two¹² B  Then, therefore 12 offset bits
Total number of $.25 needed to address a folio frame = 32 – 12 = twenty
It ways out of 32 bit Virtual addresses xx bits volition be used for indexing.

If at that place are '10' cache lines in a set and then information technology is called x-manner fix associative
4-way set up associative ways there are 4 enshroud lines in a set

Number of sets in cache = 128/4 = 32 = 2⁵= 5 bits
So, Therefore 5 bits are needed to address a set,
15 (20 – v) bits are used for defining tag .
4KB folio defines so start = 12 bits

If the page size in a 32-flake machine is 4K bytes then the size of the folio tabular array is

A	ane M bytes
B	2 M bytes
C	four M bytes
D	four 1000 bytes

Question vi Caption:

Given,
Physical address (PA) =32bit
Logical address (LA) = 32bit
Page size=4KB = two² * 2^ten B =ii¹² B (1k =2^x)
Page tabular array contains frame number + boosted bits (valid/invalid, Protection chip etc.)
Folio table for 32-fleck address infinite with 4K byte pages has 2³² / two¹² = two²⁰ entries
Page tabular array size =( Number of entries in page table ) * ( page table entry size )
Page tabular array size =2 ²⁰ × twenty bit
Page table size =4 MB(approximately).

Consider a 32-bit machine where 4-level paging scheme is used. If the striking ratio to TLB is 98%, and it takes 20 nanosecond to search the TLB and 100 nanoseconds to access the main retention what is effective memory access time in nanoseconds?

A	126
B	128
C	122
D	120

Question vii Explanation:

Effective Memory access Time, (Consume)

= H_TLB * T_TLB + (i - H_TLB)[ T_TLB + N*T_thousand] + T_chiliad]

where,
H_TLB = hit ratio of TLB
T_TLB = search time of TLB
T_thousand = Retentiveness access time
N= Number of Levels

Given,
Due north=four
H_TLB = 98%=0.98
T_TLB =  20
T_m = 100

And then,
Effective Memory access Time,(Swallow)
= H_TLB * T_TLB + (i - H_TLB)[ T_TLB + 4*T_thousand] + T_m]
Eat = (0.98 *xx) + 0.02(20 + 400) + 100
Eat = 19.half-dozen + 8.iv + 100
Consume = 128 ns

Consider a logical address infinite of eight pages of 1024 words each, mapped onto a concrete memory of 32 frames. How many bits are there in the concrete address and logical address respectively?

A	5, 3
B	x, 10
C	15, 13
D	15, 15

Question eight Explanation:

****Nosotros know that page and frame both accept the aforementioned size***

Concrete Memory take 32 frames = 2⁵
Size of word 1024 = 2¹⁰
Size of physical address space = Number of frames × Frame size
Size of physical address space =ii⁵× 2¹⁰= ii¹⁵
»» Number of required bits in the physical address =xv

Logical Memory have 8 pages = 2^three
Size of word = ii^x
Size of logical accost space = 2^m
= Number of pages × folio size
= 2³ × 2^ten = 2¹³
»» grand=13 bit
»» Number of required bits in the logical address = xiii bits

In a 64-chip machine, with two GB RAM, and viii KB folio size, how many entries volition be in that location in the page table if it is inverted?

A	218
B	220
C	two33
D	two51

Question 9 Explanation:

In Inverted folio table, the number of entries is equal to the number of frames in the main memory. Inverted page table stores the paging information of all the processes in a unmarried page table. A unproblematic inverted table stores one folio entry per physical page(frame)

Given data,
Memory size = 2 GB = 2³¹
Page size = 8 KB = 2¹³
Number of Page tabular array entries in inverted page table
= 2³¹/ii^xiii = 2¹⁸

Consider the following segment table in the partitioning scheme:

What happens if the logical address requested is Segment ID 2 and commencement 1000?

A	Fetches the entry at the physical address 2527 for segment Id2
B	A trap is generated
C	Deadlock
D	Fetches the entry at showtime 27 in Segment Id 3

Question 10 Explanation:

Given Segment-two base address is 1527 and limit address is 498
So it can only admission the retentiveness location from 1527 to 1527 + 498 = 2025
If the process tries to access the memory with offset 1000 then a sectionalisation mistake trap will be generated.

Dingy bit is used to indicate which of the following?

A	A page fault has occurred
B	A folio has corrupted data
C	A page has been modified after being loaded into cache
D	An illegal access of folio

Question 11 Caption:

Dirty bit

• A dirty chip or modified chip is a bit that is associated with a cake of estimator memory and indicates whether or not the corresponding block of memory has been modified.
• The dirty fleck is fix when the processor writes to (modifies) this memory. The bit indicates that its associated block of retentivity has been modified and has not been saved to storage yet.
• When a block of memory is to exist replaced, its corresponding muddied fleck is checked to see if the block needs to be written back to secondary memory before being replaced or if it can simply be removed.
• Dirty $.25 are used by the CPU enshroud and in the page replacement algorithms of an operating system.
• Example : When a page is modified inside the cache and the changes need to exist stored back in the main retentiveness, the valid bit is set to 1 then as to maintain the tape of modified pages.

What is the size of the physical accost space in a paging system which has a page table containing 64 entries of 11 bit each (including valid and invalid fleck) and a page size of 512

A	twoxi
B	215
C	ii19
D	220

Question 12 Caption:

Given data,
Folio table entries = 64 entries
Page size = 512 bytes
Page table entry size =11 $.25

Without valid/invalid bit
page table entry size is 11 $.25 to address each page frames
So with 11 bits there are two^xi frames available
Number of frames = ( Concrete address space / Frame size )
We know that frame size and page size both are aforementioned size
Physical address space = ( Number of frames* Frame size)
Physical address space = 2^xi* 512 byte == 2^eleven* 2⁹ byte = 2^xx Bytes

With valid/invalid bit
Paging $.25 = xi – 1 = x (Every bit one valid scrap is also included)
Therefore x bits are remaining for addressing each folio frames.
1 bit is to identify page is valid or invalid.
We know that frame size and folio size both are aforementioned size
Concrete address space = ( Number of frames* Frame size)
Physical address space = 2¹⁰ * 512 byte =  two^ten * ii⁹ byte =2¹⁹ bytes.

Using the folio tabular array shown beneath, interpret the physical address 25 to virtual address. The address length is 16 bits and folio size is 2048 words while the size of the physical retentiveness is four frames.

              Page   Nowadays(1-In 0-out)   Frame              0       1                     3 1       i                     2 2       1                     0 3       0                     -

A	25
B	6169
C	2073
D	4121

Question 13 Explanation:

Given,
Virtual address size = 16 bits
Folio size = 2¹¹ bytes.
Number of pages = 2¹⁶/2^eleven = 2^xvi-11 =2^five

We know that
Physical address = (Number of frames) * (Size of each frame)
Physical accost = 4 * 2¹¹ = 2² * ii¹¹
Physical address = 2¹³

Concrete accost representing in binary format in 13 bits
(25)₁₀ = ( 0000000011001) _two
Here first ii bits represent frame number and another 11 $.25 correspond the get-go
within the page : (00 00000011001)_two

Co-ordinate to the page table : frame 00 is mapped on with page number 2
Folio number 2 = (00010)_ii
Kickoff within the page = (00000011001)₂
Hence, 16 bit virtual address = (00010 00000011001)_ii = (4121)₁₀

In a paged retentiveness, the page hit ratio is 0.40. The fourth dimension required to access a page in secondary retention is equal to 120 ns. The time required to access a folio in primary memory is 15 ns. The average time required to access a folio is

A	105
B	68
C	75
D	78

Question 14 Caption:

Given,
Page Hit Ratio is = 0.forty
Secondary Memory Access Time=120 ns
Primary Memory Admission Time=xv ns
Miss Ratio =i – hit ratio
Average access fourth dimension= ?

Average access time = hit ratio * primary memory access fourth dimension + (i – hit ratio) * secondary retentivity access fourth dimension

Boilerplate access time = 0.4 * 15 + 0.half dozen * 120
Boilerplate admission time = 6 + 72
Average access fourth dimension = 78.

In a multi-user operating arrangement, 30 requests are fabricated to employ a particular resource per hour, on an boilerplate. The probability that no requests are made in 40 minutes, when arrival pattern is a poisson distribution, is

A	E-15
B	i - eastward-15
C	one - e-twenty
D	E-20

Question 15 Explanation:

Which of the following statements are true ?
(a) External Fragmentation exists when there is enough total memory space to satisfy a request but the available space is contiguous.
(b) Memory Fragmentation tin be internal every bit well as external.
(c) Ane solution to external Fragmentation is compaction.

A	(a) and (b) only
B	(a) and (c) only
C	(b) and (c) simply
D	(a), (b) and (c)

Question 16 Explanation:

Statement(A) : Faux
External Fragmentation exists where there is enough total memory infinite to satisfy a request just available infinite is not face-to-face.

Statement(B) : True
Retention Fragmentation tin can be internal as well as external.

Statement(C) : Truthful
One solution to external Fragmentation is compaction or shuffle retentivity contents.
Best Fit Block Search is the solution for internal fragmentation

Page information in memory is too called equally Page Table. The essential contents in each entry of a folio table is/are

A	Page Access data
B	Virtual Page number
C	Folio Frame number
D	Both virtual page number and Page Frame Number

Question 17 Explanation:

• Page information in retentiveness is likewise chosen as Page Tabular array
• A page table entry must contain Page frame number.
• Virtual page number is typically used every bit index in folio table to get the corresponding page frame number.

Consider a virtual folio reference string one, 2, 3, 2, 4, 2, 5, 2, iii, 4. Suppose LRU page replacement algorithm is implemented with 3 page frames in principal retentiveness. Then the number of page faults are

A	five
B	vii
C	9
D	x

Question 18 Caption:

Given String,
ane, ii, 3, 2, 4, 2, 5, 2, iii, 4
Total number of page faults are vii

If there are 32 segments, each of size ane Grand byte, and so the logical address should have

A	13 bits
B	14 bits
C	15 bits
D	sixteen bits

Question 19 Explanation:

Given information,
Number of segment = 32 = 2^five
Size of each segment = 1K bytes =ii¹⁰
Size of Logical address space = Number of segment * Size of each segment
Size of Logical address infinite = ii⁵ * 2¹⁰
Size of Logical address infinite = two¹⁵ =32kB
Number of bits required to correspond Logical address space = fifteen $.25

Step by footstep explanation :

To specify a particular segment v $.25 are required.
we tin written 32 as two^v = 32 = So, v bits are required.

Size of each segment = 1K bytes
nosotros tin can written 1k = 2^x
10 $.25 are required to stand for each segment

To select a particular byte later selecting a page/segment  we require 10+5=  xv bits
So Full is 10+five =xv

Note :
Yard=2¹⁰
Grand =two²⁰
Grand=2³⁰

How many wires are threaded through the cores in a coincided-current core retentivity?

A	ii
B	3
C	4
D	6

Question 20 Explanation:

• Early on systems used to have four wires: 10, Y, Sense, and Inhibit, but later cores combined the latter two wires into one Sense/Inhibit line.
• Each toroid stored ane bit (0 or ane).
• Ane fleck in each plane could be accessed in one cycle, so each auto word in an assortment of words was spread over a "stack" of planes.
• Each plane would dispense i bit of a word in parallel, allowing the full word to be read or written in one wheel.

Refer : https://en.wikipedia.org/wiki/Magnetic-core_memory

Which access method is used for obtaining a record from cassette tape?

A	Direct
B	Sequential
C	Random
D	Parallel

Question 21 Explanation:

• Tape Drive – Sequential Accessing method
• Cassette Tape – Sequential Accessing method
• Hard Disk – Both Random and Sequential Accessing methods

A CPU generates 32 bit virtual addresses. The page size is 4KB The processor has a Translation Lookaside Buffer(TLB) which can concur a total of 128 page table entries and is 4-way set up associative. The minimum size of the TLB tag is

A	xi $.25
B	13 bits
C	15 bits
D	20 bits

Question 22 Explanation:

Given information,
Virtual addresses = 32 bit = 2⁵ flake,
Page size =4 KB=2¹² B,
TLB can hold a total of 128 page table entries
4-way set up associative,

Size of a page = 4KB = nosotros can write as 2¹² B  So, therefore 12 get-go bits
Total number of bits needed to accost a folio frame = 32 – 12 = 20
Information technology means out of 32 bit Virtual addresses 20 bits will be used for indexing.

If there are 'x' cache lines in a set then it is called ten-way set associative
4-way ready associative means there are 4 cache lines in a set

Number of sets in cache = 128/4 = 32 = 2⁵= 5 bits
And so, Therefore 5 bits are needed to address a set,
xv (20 – v) $.25 are used for defining tag .
4KB page defines then offset = 12 $.25

Consider a disk pack with 32 surfaces, 64 tracks and 512 sectors per pack. 256 bytes of information are stored in a chip serial style in a sector. The number of bits required to specify a item sector in the deejay is

A	19
B	20
C	18
D	22

Question 23 Caption:

Given,
Number of surfaces = 32(2⁵)
Number of tracks per surface = 64(two⁶)
Number of sectors per track = 512(ii⁹)
Number of bytes per sector = 256 bytes(2^eight)
Total number of sectors
= Total number of surfaces* Number of tracks per surface* Number of sectors per track
=32 * 64 * 512
=(2⁵) * (two^half-dozen)  * (2^ix)
=5+6+9
=20 bits
To place each sector uniquely  we crave 20 $.25

If there are 32 segments, each size 1K bytes, so the logical address should take

A	xiii bits
B	14 bits
C	15 $.25
D	xvi $.25

Question 24 Explanation:

Given data,
Number of segment = 32 = ii^v
Size of each segment = 1K bytes =2¹⁰
Size of Logical accost space = Number of segment * Size of each segment
Size of Logical address space = 2⁵ * 2^x
Size of Logical address space = 2¹⁵ =32kB
Number of bits required to stand for Logical address space = 15 $.25

Footstep by step explanation :

To specify a particular segment v bits are required.
we can written 32 equally ii^v = 32 = And then, v bits are required.

Size of each segment = 1K bytes
we can written 1k = two¹⁰
10 bits are required to correspond each segment

To select a particular byte after selecting a page/segment  we require ten+5=  15 bits
So Total is x+5 =15

Annotation :
K=ii^x
Grand =2^twenty
G=two³⁰

Increasing the RAM of a computer typically improves performance considering:

A	Virtual Memory increases
B	Larger RAMs are faster
C	Fewer folio faults occur
D	Fewer segmentation faults occur

Question 25 Caption:

• A page mistake occurs when a plan attempts to access a block of memory that is non stored in the physical retentiveness, or RAM.
• The mistake notifies the operating organisation that it must locate the data in virtual memory, so transfer information technology from the storage device, such as an HDD or SSD, to the system RAM.
• Increasing the physical RAM on your organization could produce fewer folio faults, even though designing your application differently volition do much better than adding RAM.
• In general Decrease the physical RAM on your machine could result in more than page faults

Muddy chip for a page in a page tabular array

A	Helps avoid unnecessary writes on a paging device
B	Helps maintain LRU information
C	Allows only read on a page
D	None of the to a higher place

Question 26 Explanation:

Dirty scrap for a page in a page table Helps avert unnecessary writes on a paging device

• A dirty bit or modified bit is a bit that is associated with a block of reckoner retentivity and indicates whether or non the corresponding block of memory has been modified.
• The dirty bit is set when the processor writes to (modifies) this retention. The bit indicates that its associated block of memory has been modified and has not been saved to storage withal.
• When a block of memory is to exist replaced, its corresponding muddied bit is checked to run into if the block needs to be written back to secondary retentivity before being replaced or if information technology can simply be removed.
• Dirty $.25 are used by the CPU cache and in the page replacement algorithms of an operating arrangement.
• Example : When a folio is modified inside the cache and the changes need to be stored back in the master retentiveness, the valid chip is set to i so as to maintain the record of modified pages.

In a computer system, memory mapped admission takes 100 nanoseconds when a page is plant in TLB In example the page is not TLB, it takes 400 nanoseconds to access. Bold a hit ratio of 80%, the constructive access time is:

A	120ns
B	160ns
C	200ns
D	500ns

Question 27 Caption:

Given,
Hit ratio = H = eighty % = 0.8
Miss ratio = (ane – H) = 20 % = 0.two
TLB access time = 100ns
Principal Memory access time = 400ns
Folio is found = (T + M) = 100 ns
Page is not found = (T + 2 × M) = 400 ns

Formula:
Effective memory access time (Swallow) =
TLB_Miss_Time * (one- hit_ratio) + TLB_hit_time * hit_ratio

Calculation:
EAT = 0.8*100+0.2*400
=fourscore + 80
= 160

The following diagram depicts a______cell.

A	Storage
B	Mobile
C	Memory
D	Register

Question 28 Explanation:

• The memory cell is the central building block of calculator retentiveness. The memory prison cell is an electronic circuit that stores ane chip of binary data and it must be set to shop a logic 1 (loftier voltage level) and reset to store a logic 0 (depression voltage level).
• Its value is maintained/stored until it is changed by the set/reset process. The value in the retention cell can exist accessed by reading it.
• computer memory is a device or system that is used to shop data for immediate use in a computer or related computer hardware and digital electronic devices.

What is coalescing?

A	Information technology is a second strategy for allocating kernel retention
B	The buddy system allocates memory from a fixed size segment consistency of physically contiguous pages
C	Kernel retention is often allocated from a free retention puddle unlike from the listing used to satisfy ordinary user mode processes
D	An advantage of the buddy arrangement is how rapidly adjacent buddies can be combined to form larger segments using this technique

Question 29 Caption:

Each process is contained in a single department of retentivity that is contiguous to the section containing the adjacent procedure is chosen

A	Contiguous retentivity​ ​ protection
B	Contiguous path name
C	Definite path name
D	Indefinite path proper name

Question 30 Explanation:

• In face-to-face retentivity allocation each procedure is contained in a single contiguous block of retentivity. Memory is divided into several fixed size partitions.
• Each partition contains exactly i procedure. When a partition is free, a process is selected from the input queue and loaded into it.
• The free blocks of memory are known as holes. The set up of holes is searched to determine which hole is all-time to allocate.

Both the first fit and best fit strategies for memory allocation suffer from

A	External fragmentation
B	Internal fragmentation
C	fifty-per centum rule
D	Segmentation

Question 31 Explanation:

The simplest, but well-nigh expensive approach to introductory redundancy is duplicate to every disk. This technique is called

A	Swap space
B	Mirroring
C	Folio slots
D	None of these

Question 32 Explanation:

Copying a process from retentivity to deejay to allow infinite for other processes is called___

A	Demand paging
B	Deadlock
C	Folio fault
D	Swapping

Question 33 Explanation:

The segmentation memory direction scheme suffers from:

A	External fragmentation
B	Internal fragmentation
C	Starvation
D	Ageing

Question 34 Explanation:

Correct answer is External fragmentation

Which of the post-obit technique allows execution of programs larger than the size of physical memory?

A	Thrashing
B	DMA
C	Buffering
D	Need Paging

Question 35 Explanation:

Virtual memory is a retentiveness management scheme that allows the execution of processes that may not be completely in main memory. In other words, virtual retention allows execution of partially loaded processes. Equally a outcome user programs tin be larger than the physical memory.

An address in the memory is called

A	Concrete accost
B	Logical address
C	Retentiveness address
D	Discussion address

Question 36 Caption:

The mechanism that brings a page memory only when it is needed in___

A	Page replacement
B	Segmentation
C	Fragmentation
D	Demand paging

Question 37 Explanation:

Consider the post-obit statements
S1: a small page size causes big page tables
S2: Internal fragmentation is increase with minor pages
S3: I/O transfers are more efficient with large pages
Which of the following is true?

A	S1 is true and S3 is false
B	S1 and S2 are true
C	S2 and S3 are true
D	S1 is true and S2 is simulated

Question 38 Explanation:

S1: A small page size causes big page tables - Truthful
Smaller page size ways more than pages required per process. It means large page tables are needed.

S2: internal fragmentation is increased with pocket-sized pages- False
Internal fragmentation means when process size is smaller than the bachelor infinite. When pages are minor, then available space becomes less and there will exist less chances of internal fragmentation.

S3: I/O transfers are more efficient with large pages- True
An I/O system is required to take an application I/O asking and ship it to the concrete device. Transferring of I/O requests are more efficient with large pages.

Starting time fit and all-time fit strategies for retentiveness allotment suffer from ____ and _____ fragmentation, respectively.

A	Internal,internal
B	Internal,external
C	External,external
D	External,internal

Question 39 Explanation:

In a paging system, information technology takes xxx ns to search translation Lookaside Buffer (TLB) and 90 ns to access the main memory. If the TLB striking ratio is lxx%, the effective retention access time is :

A	48ns
B	147ns
C	120ns
D	84ns

Question 40 Explanation:

Effective retentivity access(EMA)=
Hitting ratio * (TLB access time + Main retentiveness access time) + (1-Hit ratio) * (TLB access time + (50+1) * main retentiveness time)
Where,
Fifty = Number of levels of page table
Miss Rate = (1-Hit ratio)
Note : This formula is valid simply when there are no page faults

Given,
Number of levels of page table (L) = 1
TLB access time = 30 ns
Main retention admission time = 90 ns
TLB Hit ratio = 70% = 0.7
EMA = ?
EMA =Hit ratio*(TLB access time + Main retentivity access time) +(one-Hit ratio) * (TLB access time + ii * primary retentivity fourth dimension)
EMA=0.seven*(thirty+90)+0.3(thirty+(2*90))
=0.7*120 + 0.iii(thirty+(180))
=0.7*120 + 0.iii*210
= 84 + 63
= 147 ns

A specific editor has 200 Chiliad of program text, 15 K of initial stack, fifty K of initialized data, and 70 Thou of bootstrap code. If v editors are started simultaneously, how much physical retentiveness is needed if shared text is used ?

A	1135 G
B	335 K
C	1065 Thou
D	320 K

Question 41 Explanation:

Given,
Program Text = 200 Thou
Initial stack = 15 K
Initialized data=50 K
Bootstrap code=70 K
Number of editors = 5
concrete memory is needed if shared text is used = ?
Since 5 editors started simultaneously On 200k of programme text along with 15 Thou of initial stack, 50 Yard of initialized data, and seventy Chiliad of bootstrap code.
Full concrete memory needed = Program Text + Initial stack + Initialized information + Bootstrap code
Total physical memory needed = = 200k + xv K + 50 K + 70 One thousand.
Full physical memory needed = = 335 1000

For the implementation of a paging scheme, suppose the average procedure size be 'x' bytes, the folio size be 'y' bytes, and each page entry requires 'z' bytes. The optimum folio size that minimizes the total overhead due to the page table and the internal fragmentation loss is given by

A	X/2
B	Xz/2
C	√2xz
D	√ xz/ ii

Question 42 Caption:

​To overcome difficulties in Readers-Writers trouble, which of the following statement/s is/are true?
1) Writers are given exclusive admission to shared objects
ii) Readers are given exclusive access to shared objects
3) Both readers and writers are given exclusive admission to shared objects.
Choose the correct answer from the code given below:

A	1 merely
B	Both 2 and 3
C	2 but
D	3 only

Question 43 Caption:

A Computer uses a retention unit of measurement with 256K word of 32 bits each. A binary teaching code is stored in one word of retentivity. The instruction has iv parts: an indirect bit, an performance code and a annals code function to specify ane of 64 registers and an address part. How many bits are there in functioning code, the annals code part and the address part?

A	7,7,18
B	eighteen,7,7
C	seven,6,xviii
D	6,seven,18

Question 44 Explanation:

Indirect	1 bit
Address	Given Address 256kB    28 (256kB) * 210 (1024 bytes/kB) = two18 ==18 $.25
Registers	Total 64 registers = 2half dozen = half dozen $.25
OP-code	32 - 1 - xviii - half-dozen $.25 = vii bits

Consider a system with ii level cache. Access times of Level i, Level ii cache and principal retention are 0.v ns, 5 ns and 100 ns respectively. The hitting rates of Level1 and Level2 caches are 0.vii and 0.8 respectively. What is the average access fourth dimension of the system ignoring the search time within cache?

A	twenty.75 ns
B	7.55 ns
C	24.35 ns
D	35.twenty ns

Question 45 Caption:

Ignoring search fourth dimension with in the cache argument tells u.s. to utilise parallel access( simultaneous access ).

Past default nosotros consider hierarchical access - considering that is the common implementation and simultaneous admission cache has slap-up practical difficulty
only in this question they given ignore search time within the enshroud commonly search is applicable for an associative enshroud merely here no such information given. Then, may exist they are telling to ignore the search time for L1 and merely consider the time for L2 for an L1 miss and similarly just consider memory admission fourth dimension for L2 miss. This is naught but simultaneous access.

Admission time for hierarchical access
=h1×t1+ (1-h1) h2(t1+t2) +(ane-h1)(ane-h2)(t1+t2+tm)

Access time for simultaneous admission
=h1×t1+(i−h1)h2×t2+(ane−h1)(1−h2)tm
where,
H1 = Hit rate of level 1 enshroud = 0.vii
T1 = Access fourth dimension for level ane cache = 0.v ns
H2 = Hit charge per unit of level 2 enshroud = 0.8
T2 = Access time for level ii cache = 5 ns
Hm = Hit rate of Main Retention = 1
Tm = Access fourth dimension for Chief Retentivity = 100 ns
=h1×t1+(1−h1)h2×t2+(ane−h1)(one−h2)tm
= 0.7(0.5) + 0.iii(0.8)(five) + 0.iii(0.two)(100)
= vii.55 ns

The hit ratio of a Translation Lookaside Buffer (TLAB) is lxxx%. It takes 20 nanoseconds (ns) to search TLAB and 100 ns to access chief retention. The constructive memory admission time is ______.

A	36 ns
B	140 ns
C	122 ns
D	40 ns

Question 46 Caption:

Effective memory admission(EMA)= Hit ratio * (TLB access time + Main retentivity admission time) + (ane-Hit ratio) * (TLB access time + (Fifty+1) * principal retention time)
Where,
50 = Number of levels of folio tabular array
Miss Rate = (1-Hitting ratio)
Note : This formula is valid merely when in that location are no folio faults

Given,
Number of levels of page table = 1
TLB admission time = twenty ns
Principal memory access time = 100 ns
TLB Hit ratio = 80% = 0.viii
TLB Miss ratio= 1 – 0.8= 0.2

Effective Memory Access Time
= 0.viii x { 20 ns + 100 ns } + 0.two x { 20 ns + (i+i) x 100 ns }
= 0.8 x 120 ns + 0.2 + 220 ns
= 96 ns + 44 ns
= 140 ns

In a paged retentivity, the page hit ratio is 0.40. The time required to access a folio in secondary retention is equal to 120 ns. The time required to access a page in chief retention is 15 ns. The average time required to access a page is .

A	105
B	68
C	75
D	78

Question 47 Explanation:

Given,
Page Hit Ratio is = 0.xl
Secondary Retentivity Access Time=120 ns
Master Memory Admission Time=15 ns
Miss Ratio =i – hit ratio
Average access time= ?

Average access time = hit ratio * primary memory access time + (i – hit ratio) * secondary memory access fourth dimension

Boilerplate access fourth dimension = 0.4 * fifteen + 0.6 * 120
Average access time = half-dozen + 72
Average admission time = 78.

Which of the post-obit statements are true ?
(a) External Fragmentation exists when there is plenty full memory space to satisfy a request simply the available infinite is contiguous.
(b) Memory Fragmentation can be internal as well as external.
(c) Ane solution to external Fragmentation is compaction.

A	(a) and (b) only
B	(a) and (c) simply
C	(b) and (c) only
D	(a), (b) and (c)

Question 48 Caption:

Statement(A) : False
External Fragmentation exists where there is enough total memory infinite to satisfy a request just available space is not face-to-face.

Statement(B) : True
Memory Fragmentation can exist internal as well as external.

Argument(C) : Truthful
One solution to external Fragmentation is compaction or shuffle retentivity contents.
Best Fit Cake Search is the solution for internal fragmentation

Page information in memory is also chosen as Page Table. The essential contents in each entry of a page tabular array is/are .

A	Folio Admission information
B	Virtual Folio number
C	Page Frame number
D	Both virtual page number and Page Frame Number

Question 49 Explanation:

• Page information in memory is also called equally Folio Table
• A page table entry must contain Page frame number.
• Virtual folio number is typically used as index in page table to get the respective page frame number.

Given memory partitions of 100 Thou, 500 K, 200 Thou, 300 Thou and 600 Chiliad (in order) and processes of 212 Thousand, 417 G,112 Thousand, and 426 K (in gild), using the first-fit algorithm, in which partition would the process requiring 426 G be placed ?

A	500 Yard
B	200 G
C	300 Chiliad
D	600 Yard
E	NONE

Question 50 Explanation:

Which of the following retentivity resource allotment scheme suffers from external fragmentation ?

A	Division
B	Pure need paging
C	Swapping
D	Paging

Question 51 Explanation:

• Division is gratuitous of internal fragmentation merely Suffers from external fragmentation.
• In Paging There is no external fragmentation simply internal fragmentation exists.
• Swapping is a mechanism in which a process can be swapped temporarily out of main memory (or movement) to secondary storage and make that retention available to other processes. At some subsequently time, the system swaps back the process from the secondary storage to main memory.

The virtual accost generated past a CPU is 32 bits. The Translation Lookaside Buffer (TLB) tin concur total 64 page table entries and a four-style set associative (i.due east. with four-cache lines in the set). The page size is 4 KB The minimum size of TLB tag is

A	12 bits
B	15 bits
C	16 $.25
D	twenty $.25

Question 52 Caption:

Virtual Address = 32 bits
Page size = 4 KB = ii¹² Bytes
Number of bits needed to address the page frame = 32-12=xx bits
Translation Look-aside Buffer (TLB) can agree 64 folio table entries with 4-way gear up associative
Number of sets = 64/4 = sixteen(16=ii^iv bits.)
Therefore 4 $.25 are needed to address a gear up
So Tag bits = twenty - 4 = 16 bits.

Consider a logical accost space of 8 pages of 1024 words mapped with retention of 32 frames. How many bits are there in the physical address ?

A	9 bits
B	xi $.25
C	13 $.25
D	15 bits

Question 53 Caption:

****We know that page and frame both have the same size***

Concrete Memory have 32 frames = 2⁵
Size of word 1024 = 2¹⁰
Size of physical address space = Number of frames × Frame size
Size of physical address space =ii⁵× 2¹⁰= two¹⁵
»» Number of required bits in the physical address =fifteen

Logical Memory have eight pages = 2^three
Size of word = two¹⁰
Size of logical address space = 2^m
= Number of pages × page size
= two³ × ii^ten = 2^thirteen
»» g=13 bit
»» Number of required bits in the logical address = xiii bits

Allow the folio fault service time be ten millisecond(ms) in a figurer with boilerplate memory access fourth dimension beingness 20 nanosecond(ns). If 1 folio mistake is generated for every x⁶ retentiveness accesses, what is the constructive access time for memory ?

A	21 ns
B	23 ns
C	30 ns
D	35 ns

Assume Due north segments in memory and a page size of P bytes. The wastage on account of internal fragmentation is :

A	NP/ii bytes
B	P/ii Bytes
C	N/2 Bytes
D	NP Bytes

Question 55 Explanation:

Given,
Total Segments = N
Folio size = P bytes
Wastage on account of internal fragmentation = (Due north*P) / ii bytes

Assertion (A) : Bit maps are non ofttimes used in retentiveness management.
Reason (R) : Searching a bitmap for a run of given length is a slow operation.

A	Both (A) and (R) are true and (R) is correct explanation for (A)
B	Both (A) and (R) are true only (R) is not correct explanation for (A)
C	(A) is truthful (R) is false
D	(A) is false (R) is true

Suppose it takes 100 ns to admission a folio tabular array and 20 ns to access associative retention with a 90% hitting charge per unit, the average access fourth dimension equals :

A	20 ns
B	28 ns
C	ninety ns
D	100 ns

Question 57 Explanation:

Given information,
Folio tabular array access time = 100 ns
Associative memory admission time = 20 ns
Striking rate = 90% = 0.9
Miss ratio = (1-Hitting ratio)=1-0.ix=0.1
Access time = Hit ratio * Associative memory admission fourth dimension + Miss ratio * Folio Table admission time
Access time= 0.nine* 20 + (1-0.ix)*100
Access time =28ns

Variable partition retention management technique with compaction results in :

A	Reduction of fragmentation
B	Minimal wastage
C	Segment sharing
D	None of the above

Question 58 Caption:

• One mode to remove external fragmentation is compaction. When dynamic partitioning is used for memory allotment then external fragmentation tin exist reduced by merging all the costless retentiveness together in one large block.
• This technique is also chosen defragmentation. This larger block of memory is and then used for allocating space according to the needs of the new processes.

A page fault

A	Is an mistake specific folio.
B	Is an access to the page not currently in retentiveness.
C	Occur when a page programme occur in a page retentiveness.
D	Page used in the previous page reference.

Question 59 Explanation:

Page fault
When we want to load the folio on the retentiveness, and the page is not already on retentivity, then it is called a page error. The folio fault is also called page miss.

Page Hit
When nosotros want to load the page on the memory, and the page is already available on memory, so it is called page hit.

Cache Hit
Cache Memory is a small memory that operates at a faster speed than physical memory and nosotros always go to cache before nosotros go to physical memory. If we are able to locate the corresponding give-and-take in cache retentiveness inside the cache, its called cache hit and nosotros don't even need to get to the physical retention.

Cache Miss
It is only afterward when mapping to cache memory is unable to find the corresponding cake(block similar to concrete memory page frame) of memory inside enshroud ( called cache miss ), then we go to concrete memory and practice all that process of going through page table or TLB.

NOTES :

A plan is located in the smallest bachelor hole in the memory is _________

A	All-time – fit
B	First – fleck
C	Worst – fit
D	Buddy

Question sixty Explanation:

Suppose it takes 100 ns to access folio table and 20 ns to admission associative retentiveness. If the average access fourth dimension is 28 ns, the corresponding hit rate is :

A	100 per centum
B	90 percentage
C	80 percent
D	70 pct

Question 61 Explanation:

Given data,
Page table access time = 100 ns
Associative memory access time = xx ns
Average Access time = 28 ns
Hitting rate = 10
Miss ratio = (one-Hit ratio)=i-x

Boilerplate Admission fourth dimension = Hit ratio * Associative memory admission time + Miss ratio * Folio Tabular array access time

28ns = x*20ns + (1-10)*100ns
28 = 20x + 100-100x
28 = 100-80x
80x= 100-28
ten=72/80=0.9
Hit ratio = xc%=0.9

There are 61 questions to complete.

If We Are Using Pages Of Size 4kb, How Many Bits Are Needed For Displacement Into A Page?,

Source: https://academyera.com/memory-management-operating-systems-topic-wise-gate-cs-solved-questions

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